The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for
presentation of innovative research in all aspects of low power electronics and design, ranging from process
technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level
design, and optimization, to system software and applications. Specific topics include, but are not limited to, the
following three main tracks and sub-areas:

Track 1. Technology, Circuits, and Architecture

1.1. Technologies and Circuits
Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical,
printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean
and quantum/quantum-inspired compute models. Low-power circuits for logic, memory, reliability, yield, clocking,
resiliency; low-power analog/mixed-signal circuits for wireless, RF, MEMS, ADC/DAC, I/O, PLLs/DLLs, DC-DC
converters; energy-efficient circuits for emerging applications (e.g., neuromorphic, biomedical, in-vitro sensing,
autonomous); circuits using emerging technologies; cryogenic circuits. DTCO for low power; combinatorial
optimizers (Ising machine). AI/ML-based circuit optimization; circuit architecture for power-efficient AI
applications.

1.2. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special
purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and
non-conventional computing. System technology co-optimization (STCO) for low power. AI/ML-assisted logic
optimization and architecture exploration. Power efficient architecture for AI.

Track 2. EDA, Systems, and Software

2.1. CAD Tools and Methodologies
CAD tools, methodologies, and AI/ML-based approaches for low power and thermal-aware design
(analog/digital). AI/ML for acceleration of IP block design convergence. Power estimation, optimization, reliability,
and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register
transfer, behavior, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems,
Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level
power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired
computing to power-aware system and platform design.

2.3. Software and Applications
Energy-efficient, energy/thermal-aware software and application design, including scheduling and management,
power optimization through HW/SW co-design, and emerging low-power AI/ML applications.

Track 3. Crosscutting Topics

3.1. AI/ML Hardware and Systems
Low-power AI/ML HW techniques including approximations, application-driven optimizations, energy-efficient
accelerations, and neuromorphic computing; energy-efficient HW and systems for generative AI applications
(LLMs, diffusion models)

3.2. Emerging and Next-Generation Computing
Energy-efficient in-memory/near-memory/in-storage computing; quantum computing; analog/mixed-signal
computing; optical computing; bio-inspired computing

3.3. Hardware and System Security
Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators),
nano-electronics security, supply chain security, IoT security and AI/ML security; confidential computing; energy-
efficient approaches to system security.

Track 4. Industrial Design Track

This track solicits papers to reinforce interaction between the academic research community and industry.
Industrial Design track papers have the same submission deadline as regular papers and should focus on similar
topics but are expected to provide a complementary perspective to academic research by focusing on challenges,
solutions, and lessons learnt while implementing industrial-scale designs.