Beside the conference main theme, the ARCS’25 conference welcomes all contributions on hardware architectures, as well as their programming models, software stacks (operating systems, compilers...), their insertion into computing systems, and the challenges to port optimized code:

    Hardware Architectures
        Reconfigurable architectures
        System‑on‑chip
        Distributed systems
        High performance systems
        Heterogeneous multi‑& many‑core architectures
        Hybrid CPU‑GPU and CPU‑QPU architectures
        HPC‑workload specific accelerator architectures
        Architectures for real‑time and mixed‑criticality systems
        Coarse‑/fine‑grained reconfigurable architecture
        Flexible I/O support
        Using new non‑volatile memory for energy‑efficient architectures
        New smart network technologies (e.g. Smart‑NICs, SmartSwitches)
        Advanced computing architectures

    Programming Models and Runtime Environments
        Programming on novel HPC chip architectures
        HPC programming models for heterogeneous computing
        Hybrid CPU‑QPU programming and experiments
        Tools to monitor and to optimize the power consumption of HPC architecture
        Operating systems, programming models, algorithms, and data structures for heterogeneous HPC architectures
        Operating systems, hypervisors and middleware for homogeneous and heterogeneous multi‑/many‑core computing platforms
        System management including but not limited to scheduling, memory management, power/thermal management, and RTOS
        Domain‑specific languages and programming models
        Architecture specific code generation/optimization
        Architectural simulation

    Cross-sectional Topics
        Near-memory and in-memory computing
        Memory and network compression technologies
        Organic computing
        Pervasive systems
        Autonomous systems
        Approximate Computing
        Mixed-criticality systems
        Support for safety and security
        Hardware in the loop simulations
        Optimization and performance analysis